Mobile devices, such as but not limited to personal data appliances, cellular phones, radios, pagers, lap top computers, and the like are required to operate for relatively long periods before being recharged. These mobile devices usually include one or more processors as well as multiple memory modules and other peripheral devices.
In order to reduce the power consumption of mobile devices various power consumption control techniques were suggested. A first technique includes reducing the clock frequency of the mobile device. A second technique is known as dynamic voltage scaling (DVS) or alternatively is known as dynamic voltage and frequency scaling (DVFS) and includes altering the voltage that is supplied to a processor as well as altering the frequency of a clock signal that is provided to the processor in response to the computational load demands (also referred to as throughput) of the processor. Higher voltage levels are associated with higher operating frequencies and higher computational load but are also associated with higher energy consumption.
U.S. patent application 20040052098 of Burstein et al., titled “digital voltage using current control”; U.S. patent application 20030139927 of Gabara, et al., titled “Block processing in a maximum a posteriori processor for reduced power consumption”; U.S. patent application 20020000797 of Burstein et al., titled “Switching regulator with capacitance near load”; U.S. patent application 20040025068 of Gary et al., titled “Methodology for coordinating and tuning application power”; U.S. patent application 20010038277 of Burstein et al., titled “Digital voltage regulator using current control”, and “A Dynamic Voltage Scaled Microprocessor System”, T. D. Burd, T. A. Pering, A. J. Stratakos and R. W. Brodersen, IEEE Journal Journal of solid-state circuits, Vol. 35, No. 11, November 200, all being incorporated herein by reference, provide a brief review of some dynamic voltage scaling techniques.
FIG. 1 illustrates the supply voltage that is being supplied to a processor (such as the CPU of FIG. 2) during the execution of various tasks as well during an idle period. For simplicity of explanation the supply voltage is illustrated as a sequence of ramps, and the transition periods between voltage ramps are not illustrated. The transition periods are very short, and typically do not exceed few milliseconds.
During a first time period ΔT1 11 that starts at T0 and ends at T1, the processor executes a very high throughput task and accordingly receives a very high frequency clock signal and a very high level supply voltage Vvery_high.
During a second time period ΔT2 12 that starts at T1 and ends at T2, the processor executes a high throughput task and accordingly receives a high frequency clock signal and a high level supply voltage Vhigh.
During a third first time period ΔT3 13 that starts at T2 and ends at T3, the processor executes a medium throughput task and accordingly receives a medium frequency clock signal and a medium level supply voltage Vmedium.
During a fourth time period ΔT4 14 that starts at T3 and ends at T4, the processor is idle and accordingly receives a very low frequency clock signal (or alternatively does not receive a clock signal) and a very low (even zero) level supply voltage Vvery_low.
During a fifth time period ΔT5 15 that starts at T4 and ends at T5, the processor executes a high throughput task and accordingly receives a high frequency clock signal and a high level supply voltage Vhigh.
It is noted that the voltage supplied to the processor is decreased (usually during a very short time period) at about T1, T2 and T3 and is increased at about T4.
FIG. 2 illustrates a prior art device 20 that includes multiple power consuming devices such as a central processing unit (CPU), SRAM and I/O card, collectively denoted 30, a frequency regulator 40, a voltage regulator 50, an output inductor 34 and a load capacitor 32.
The voltage regulator 50 receives a desired frequency from the frequency regulator 40, a 1 Mhz clock signal and provides a frequency error signal to a digital filter that in turn sends control signals to a FET control and drivers unit 52 that applies a pulse-width/pulse frequency modulation scheme to control a pair of power FET transistors Mn 56 and Mp 54. The gates of Mn 56 and Mp 54 are connected to the FET control and drivers unit 52, that turns them on and off in response to said modulation scheme. The source of Mp 54 is connected to a battery 60 and the drain of Mp 54 is connected to the drain of Mn 56. The drain of Mn 56 is grounded.
The drains of Mn 56 and Mp 54 are connected at an output node of the regulator. This output node is connected to a first end of an inductor 34. The other end of the inductor 34 is connected to a first end of a load capacitor 32. The second end of the load capacitor 32 is grounded. The second end of the inductor 34 is also connected to the frequency regulator 40 and to devices 30.
The load capacitor is relatively large (about 5.5 Microfarad). Typically, such as load capacitor 30 is used to smooth the voltage supplied to the processor. In various mobile devices the load capacitor is also used as a power reservoir that provides power during short supply power failure. Such a power reservoir is described at U.S. Pat. No. 6,226,556 of Itkin et al., which is incorporated herein by reference.
Referring back to the prior art device 20, the regulator 50 can increase or decrease the regulated voltage supplied to its output node, and thus may dynamically alter the voltage supplied to the CPU and other devices.
In some prior art regulators a decrement in the regulated voltage involves decreasing the charge of the load capacitor 32 by draining said charge to the ground. Thus each voltage decrement involves power loss.
The prior art device 20 also loses energy as a result of removing charge from the load capacitor to a battery bypass capacitor (not shown in FIG. 2).
There is a need to provide an efficient method and apparatus for dynamically providing regulated voltage to a processor.